A phase-locked loop (PLL) is an electronic control system that generates an oscillating signal having a fixed phase relationship (e.g., synchronized or having a fixed gap) with a reference signal. A phase-locked loop circuit automatically raises or decreases a frequency of a controlled oscillator until the frequency matches the reference signal in both frequency and phase. An all digital PLL (ADPLL) is a digital system implemented with digital logics. An ADPLL circuit may include a time-to-digital converter (TDC). The TDC is configured for sampling the oscillation signal at a predetermined resolution, and feeding the sampled signal back to the phase detector, so as to raise or lower the frequency of input signals of the ADPLL circuit.